Chip Tester de 8bit-museum.de - Reloaded

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 12:42

cacharreo escribió:
18 Oct 2020, 10:34
Para despejar posibles dudas sobre el correcto funcionamiento del IC de las pruebas, el 74LS00, he realizado comprobaciones adicionales:
There is still the problem that it doesn't stop, so there seems to be a problem with the firmware, I cannot reproduce.
You are using the same fuse settings? So no memory is reserved for a boot loader?

I am not sure why it resets. Maybe something went wrong during programming. Which programmer do you use?
Please can you do following: Go to the menu "Info" and check if the size of two databases are displayed. Then perform a self check (menu "selfcheck") if all voltages are correctly switched.
Are you using the XL6009 module (which I do not recommend, because it creates lots of noise)? You are the only person who asked for it (you also have the better RECOM module).

cacharreo escribió:
18 Oct 2020, 10:34
Imagen

el canal D0 se ha conectado a la salida de un generador de funciones programado para sacar ruido aleatorio ("cuantizado") que conectada a su vez a cada una de las entradas de las 4 puertas NAND del chip mientras que la otra entrada se ha conectado directamente a nivel alto (~+5V) para que las 4 puertas actúen como inversores (improvisados). En el analizador lógico del osciloscopio las señales D1, D2, D3 y D4 corresponden a las respectivas salidas de las 4 puertas NAND del chip. Las mismas pruebas utilizando como señal una onda cuadrada perfecta da muchos mejores resultados incluso a frecuencias mucho más altas.

Por último, aprovecho el mensaje para, como quedamos, pasarte la lista de frases en alemán que quedaron en la versión que descargué del manual en inglés.

Código: Seleccionar todo

5.5.2 Auslesen von ROM, PROM, EPROM oder EEPROMs
Einfacher Logik-Tester
Soft- und Hardware
Thanks for the picture I will check it. Maybe there it a short at one of the signals going to the ATmega. Please can you check the Zener diodes.
Maybe there is a short, so the input will always LOW. When a test stops. all voltages are switched off (Vss and Vcc). Maybe there is a short to a signal track so this lets the ATmega perform a reset?

Personally I don't think that there is a problem with the firmware, since the problem exist also with the original one.
I think there is a faulty (transistor or Zener) component, maybe soldered a wrong transistor or a wrong resistor.

Nevertheless I used the finding to do some experiments. I post next.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 12:44

Before I saw the video with the firmware, I thought about whether a chip could actually work if it was inserted the wrong way round.
And yes, it depends on the chip and the technology used, how it behaves. Let me describe some of my finds here.

In advance: There are people who, because of their narrow view of the world and poor understanding, just gossip and first blame without any evidence.
That shows stupidity. It is interesting to find out whether a chip can actually work that way.


I have just done a few experiments on this and the result is: It is possible under certain (several) conditions:

1. Requirement (structure of the chip):
=======================================
First of all, the gates must be arranged in a suitable manner so that when the chip is rotated, they are still connected.
This is not the case with the 7400, so the error should be detected with a suitable test pattern.

Let's simplify the circuit and take a chip in Diode logic with different gate positions.
see also https://en.wikipedia.org/wiki/Diode_logic

Imagen
If you use this chip, you will see that it can be used the other way around, as the gates are mirrored.


2. Requirement (technology used):
=======================================
Let's think about what a power supply is used for.

With diode technology, you can do without power supply (with two parallel diodes you have an OR gate, completely without voltage supply).
However, each diode has a voltage drop of 0.7V, i.e. after a few diodes there isn't much left. In addition, as much power must be made available at the inputs as is required at the output for control. So the power supply is used to have a reference voltage that can be used.

Now we don't have diode logic, but TTL technology, i.e. transistors. Transistors are amplifiers that are used as switches in our purpose (we have to go into saturation for this).

Let's take the following transistor (two bases, so it is an OR gate, greatly simplified):
Imagen
What happens in normal operation? Transistors (BJTs) are current controlled (not voltage controlled like (MOS)FETs).

With a low input current Ibe, a larger output current Ice is switched. In the circuits we use, the gain is not so important, but with e.g. 74xx chips, you still need an input current of 3-5mA(!) to switch cleanly. With the 74LSxx it is approx. 1-2mA.

I have already added a chapter in the manual that addresses this problem if a chip requires an increased input current of >5mA due to aging (the Chip Tester can only deliver a maximum of 5mA). Sometimes it will work, sometimes it won't.

Now, what happens if the Vcc and GND are omitted from the OR gate? That depends a lot on the chip. In the transistor example above, the OR gate will still work, but the input current does not switch Ice, but Ibe will be measurable at the output. If this is now normally loaded, the base will probably burn through, additonally a voltage drop of Ube can be measured. This transistor behaves like a diode.

What happens when you switch voltage polarity?
If there are no protective diodes (modern chips have them), the transistor is operated with the polarity reversed (i.e. C and E reversed). This works, but you do not have the full current gain and the transistor will probably not work long if it is loaded due to the different thicknesses of the layers.

I did an experiment with the 74LS00. This has a special feature, an additional inverter (NAND-gate).

In normal operation it looks like this.
Imagen
Power supply is available. Pin 1 and pin 2 are at Vcc in the picture, I measure a LOW at pin 3.

Now I remove GND:
Imagen
There is still a LOW at the output, but now at around 0.7V (remeber the 0,7V voltage drop).

Now we set pin 2 to GND:
Imagen
And, as expected, we get a HIGH. The chip also works without a correct power supply!

There are a few restrictions here, however. Due to the inverter, Vcc cannot be dispensed with and it can look different with other chips.
At least one input of another(!) gate must be connected to GND. (** more on this below). The internal structure of the chip would be interesting here to know.

If you want, you can try it out with other 74xx gates. I had limited the power supply to 10mA so that a chip would not be damaged.


And now comes the highlight:
-----------------------------
We reverse the supply voltage and see if it works:
Imagen
You can see that I applied +5V to Vss and limited the current to 5mA with 1k Ohm, Vss is not connected to Vcc. Both inputs are HIGH, the output is HIGH.

Imagen
In the picture one input is at LOW, the output is too. In this configuration we have an OR gate.

So a NAND chip operated with the wrong polarity behaves like an OR gate in this experiment ;) At least one chip from this manufacturer. Chips from different munufacturers can have completely different structures.

The inverter is missing. If you like, you can do your own experiments and look and find out under which conditions a chip behaves and how.


3. Requirement (the test pattern):
=======================================
I programmed the firmware in such a way that the test patterns only make sense if the chip is correctly positioned in the socket.

If it sits rotated in the socket, it is operated with the wrong polarity, as shown above, anything can happen.

It is also very likely that Vcc or Vss will suddenly be applied to the outputs. In a real circuit the chip will be destroyed due to overheating (due to a possible shortcut, we learned not to connect an output to a Vcc or GND), but the Tester delivers only a maximum of 5mA, not enough to damage the chip.

Let's take another look at the transistor above: If a voltage is applied to the emitter, the emitter - base/collector junction blocks, but depending on how the circuit is constructed, this voltage could trigger a base on another transistor. What happens then depends entirely on the chip.

The Chip Tester uses e.g. Pullups at the outputs of the chips in order to be able to test Open Collector components. Even this small current <100nA could switch something if the chip was inserted the wrong way round.

The NAND gate from (2, **) would then be tested as error-free in the correct position if the test pattern is structured in such a way that at least one input of another gate is always HIGH or LOW (actually it is). But who is planning test patterns for an incorrectly inserted chip?


The result also applies to all testers: If a tester or device under test is operated outside of the specification, anything can occur.

The limits of the Chip Tester are described very clearly in chapter 8 of the manual. In the next issue there is another interesting example with a 7490 (non LS type) chip. If a chip is operated outside of the specification, anything can happen (e.g. a NAND gate becomes an OR gate).

If you are doing your own experiments, you will need an oscilloscope so that the outputs are not heavily loaded. An LED may not yet light up at <1mA, but the voltage level can still be clearly seen on the oscilloscope. The Chip Tester can also detect this well due to the high-resistance inputs. If you want, you can also write your own short program to check out these tests with the help of the Tester.


I use the Tester for about three years now, and yes, there are still TTL test patterns that have not been tested using a real chip (I have not all chips available and lots of patterns I did manually using the datasheets). That can always happen and when you find such a bug I will fix it (see the changelog).

Again: No Tester can detect 100% of the possible faults. With the March-Y and March-U tests you will detect >90% of the possible faults (no signal level related faults etc., see chapter 8 again) and 99.9% of the defect chips in the wild.

The TTL tests are not so sophisticated, you will recognize also >99% of all defects when you use the Tester/Chip in its specification. When you try to test a chip that needs an input current >4-5mA you cannot expect that the chip will be tested ok even when it works fine (that is very rare, only a very few 74xx chips need so much current at their inputs).

And of course: When you do modifications at the firmware or when you modifies the hardware (e.g. using other transistors or diodes) you might also get wrong results.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 12:45

Ok, the last post has nothing to do with the problem but it causes me to do some experiments ;)

By the way, there are some people who have thought about this, e.g.
https://jeelabs.org/2013/05/08/what-if- ... index.html
and lots of more...

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 13:14

I checked two other chips:

The first video shows a TTL chip, two times in correct position, one time in wrong position:
https://videobin.org/+1cln/1j4e.html
Very interesting: The fourth(!) pattern recognized that the chip is not correct. Test 1-3 identifies the correct output.

This is a HC Chip (=CMOS, so not a BJT, which is current controlled, but voltage controlled).
https://videobin.org/+1clo/1j4f.html
The first(!) pattern finds out that the chip is not correct.

So it is really a problem with the TTL, that you can not predict what happens when the chip it is reversed powered.
The LS type has only 4 gates = 4 outputs, 2 gates are equally tested, so there are only 4 different possibilities. So there is a 1:4 chance that the pattern is exact the way that is expected, even when the chip is turned in the wrong direction. And it seems that with your chip you won the 25% chance to get the correct signals ;)

Nevertheless the test method is different: We assume that the test is ok (and inserted correctly), and when the Tester says it is defect is most likely defect. Not the way: We assume the chip is defect and only when the Tester says it is ok, it is ok.

There is a difference. In the first way we try to find a pattern where the chip behaves different what we expect. When clever chosen: You need only a few pattern to verify the functionality of a chip. The more we test the better the result.
The second approach means to do so many positive tests that you find the chip is ok. You need much more pattern to verify that it works properly then patterns used to find it works wrong. Under the assumption that you don't modify the test, e.g. by rotating the chip ;)

btw: What happens when you use a different chip in the correct/wrong position?
Última edición por slabbi el 18 Oct 2020, 13:37, editado 1 vez en total.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por cacharreo » 18 Oct 2020, 13:36

Me alegro un montón de que esto haya servido para motivar tanta experimentación (aquí lo llamamos "cacharreo").
slabbi escribió:
18 Oct 2020, 12:44
And, as expected, we get a HIGH. The chip also works without a correct power supply!
También he podido comprobarlo con el osciloscopio y el generador de funciones.
slabbi escribió:
18 Oct 2020, 12:44
So a NAND chip operated with the wrong polarity behaves like an OR gate in this experiment ;) At least one chip from this manufacturer.
De Morgan. ;)

De cualquier modo esto no debería ser una fuente de preocupación porque la variación de comportamiento, dado que la operación lógica es otra, será (o debería ser) detectada por el chip tester.
slabbi escribió:
18 Oct 2020, 12:44
By the way, there are some people who have thought about this, e.g.
https://jeelabs.org/2013/05/08/what-if- ... index.html
Esta concretamente la conocía aunque no ha sido la inspiración inicial para hacer las pruebas.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 13:52

cacharreo escribió:
18 Oct 2020, 13:36
slabbi escribió:
18 Oct 2020, 12:44
So a NAND chip operated with the wrong polarity behaves like an OR gate in this experiment ;) At least one chip from this manufacturer.
De Morgan. ;)

De cualquier modo esto no debería ser una fuente de preocupación porque la variación de comportamiento, dado que la operación lógica es otra, será (o debería ser) detectada por el chip tester.
Well, in your case the chip does not behave like an OR gate it behaves like an NAND-gate (so the tester gets the same results).

In the Tester the test condition is different from what I had on the breadboard:

Vcc supplied to GND is not really limited (the transistor can deliver 100mA without problems it depends on the internal resistance of the chip how high the current is). The same for the sink Vss.
When this is tested on a breadboard the power should also not limited (careful because in the tester the tests takes a few milliseconds which will hopefully not harm the chip).
Every output of the 74LS is connected with pullups to Vcc (the ATmega has afaik 10-20 kOhm pullups), so a small current is injected at these positions. You must simulate this is the breadboard in order to get the same results. The inputs of the 74LS are connected to ground or Vcc using an 1 kOhm resistor, so the current is limited to <5mA.

Under this condition is might be that the NAND gate will still behave as a NAND gate with very low currenty. Rember that some inputs are treated as outputs and vice versa.
E.g. Pin 1 and 2 are usually inputs, Pin 3 an output. Turning the chip lets the Tester thing that this is still the case but now the chip provides an output at Pin 1, and inputs at Pin 2 and 3, that means that the Tester injects Vcc/GND (limited to 5mA) to Pin 1 (output) and expects the result at Pin 3 (now an input and connected with an Pullup to Vcc).
I think: Because of the pullup Pin 3 will be always high. Pin 2 will change according to what the tester appliies, Pin 1 is the big question. Don't know what happens. And you have the "OR-behavior". This should be written in a truth table and check against the patterns. Maybe it fits ;)

Really interesting. Maybe worth to make some additional investigations. It would be really helpful to have the schematics of the 74LS gate used. :)

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 14:15

Maybe I got it ;)

Lets assume that the 74LS00 behaves like an OR gate in reverse position that we have following conditions:

| Pin 1               | Pin 2               | Pin 3                | 
| output of the NAND  | input A             | input B              | 
| treated as          | treated as          | treated as           | 
| input by the tester | input by the tester | output by the tester |Remark
|:-------------------:|:-------------------:|:--------------------:|:--------------------------------------------------:|
|     0               |         0           |       PU=H           |  input B is 1, input A is 0, the pattern expects H
|     0               |         1           |       PU=H           |  input B is 1, input A is 1, the pattern expects H
|     1               |         0           |       PU=H           |  input B is 1, input A is 0, the pattern expects H
|     1               |         1           |       PU=H           |  input B is 1, input A is 1, the pattern expects L

The first three are obvious: since one input is 1 the output is H because of the OR behavior
The fourth is interesting: the tester thinks that pin 3 is the output and expects a LOW there. But it is logic H because of the pullup (maybe 10uA).
That is why my video of the 74LS00 shows an error in the fourth step. So the assumption (and these considerations) seems to be correct.

In your case the the output of the tested chip is LOW which means that there is either a different behavior of the chip because of the connected output (pin 1) to Vcc, or there is an small leakage that allows to sink approx 10uA, so that the tester reads an LOW which means that the Tester cannot separate this chip from a correct inserted one.

The question is if this is in relation to the observation that the Tester makes a reset (a short on the board). The contrast or the brightness of the display will be worse if you test a TTL chip? Usually that shouldn't be the case (or only a very little because of a small voltage drop of a few millivolts).


Interesting, very interesting indeed.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por cacharreo » 18 Oct 2020, 14:47

slabbi escribió:
18 Oct 2020, 13:52
Well, in your case the chip does not behave like an OR gate it behaves like an NAND-gate (so the tester gets the same results).
En mi caso no tengo aún claro si hay o no un problema con el chip tester. Después de probar en el chip tester y ver que los daba por correctos tanto al derecho como al revés, probé con los dos chips (74LS00 y 74HC00) en la breadboard. En la práctica, si no me equivoco, probé una sola puerta NAND utilizando como entradas los pines 8 y 9 y como salida el pin 10. No usé pull-ups para la salida pero lo cierto es que no hacían nada, es decir, probando los 4 valores posibles en las dos "entradas" (pines 8 y 9) en la "salida" (pin 10) sólo obtuve un cero lógico.
slabbi escribió:
18 Oct 2020, 13:52
It would be really helpful to have the schematics of the 74LS gate used. :)
Estas son las fotografías de los dos chips (74LS00 y 74HC00) que he utilizado con idénticos resultados.

Imagen

Por último recordaría que con los chips invertidos, al terminar el test el chip tester se reinicia.
slabbi escribió:Maybe something went wrong during programming. Which programmer do you use?
Finalmente intercambié el programador con mi conocido y ahora uso el Diamex Prog-S2. No hay problema ni durante la escritura, ni durante la verificación.
slabbi escribió:You are using the same fuse settings?
Exactamente los mismos.
slabbi escribió:You are the only person who asked for it (you also have the better RECOM module).
Solo he usado el módulo # 2 con el RECOM DC-DC.
slabbi escribió:menu "Info" and check if the size of two databases are displayed.
DB1: 15B83 DB2: B8B1
slabbi escribió:Then perform a self check (menu "selfcheck") if all voltages are correctly switched.
Selftest OK
slabbi escribió:Please can you check the Zener diodes.
Todos parecen estar bien.

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por slabbi » 18 Oct 2020, 15:13

I will send you a modified firmware that applies the pullups only when a LOW is expected. Currently a pullup is applied regardless of the expected signal.

I marked this as BUGBUG some time ago but not thought about it again. It will break the possibility to test open collector outputs since these require external pullups. Perhaps I will have to add a special flags to all chips that are using OCs.

It will not solve the other problem but should help to recognize the chip to be failed with the first pattern.

Edit:
Yes, verified. It recognized the chip as faulty in the first step now.
BUT: I see that there is an internal short in the chip when inserting it the wrong way. The LS is use does not leak so much current that the Tester resets, but the display will be much darker.

When you use other chips in the correct way, does the Tester also do a reset?

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Re: Chip Tester de 8bit-museum.de - Reloaded

Mensaje por cacharreo » 18 Oct 2020, 15:57

slabbi escribió:
18 Oct 2020, 15:13
I will send you a modified firmware that applies the pullups only when a LOW is expected. Currently a pullup is applied regardless of the expected signal.
Gracias, lo probaré en cuanto lo reciba, llevo un tiempo sin comprobar el email.
slabbi escribió:
18 Oct 2020, 15:13
When you use other chips in the correct way, does the Tester also do a reset?
Cuando uso cualquier IC, incluyendo los dos de las pruebas anteriores, en su posición correcta no hay reset y sí se produce la espera después de "Again?".

He hecho otras pruebas, esta vez he utilizado un 74HCT14N pero he seleccionado la prueba del 7400 y, sorprendentemente, en el 50% de ellas el resultado es que el chip está bien (no hay reseteo tras el test). El procedimiento que uso es:

1) Conecto la alimentación
2) Espero a que desaparezca la nag screen
3) Pulso JUMP hasta llegar a 74xx Logic...
4) Pulso OK
5) Pulso OK

y hace el test para los 7400. Como cabe esperar, con la prueba específica para el 7414 no hay problemas.
Última edición por cacharreo el 18 Oct 2020, 16:47, editado 2 veces en total.

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