Hay algo que estoy leyendo en la url del proyecto en GitHub:
"Recommend using 74F-series, and update the schematic and the silkscreen accordingly. 74F-series ICs are faster and slightly cheaper than 74ALS-series"
"Add 74F573 latch for latching A8-A11 signals. This fixes the DMA issue"
Concretamente ese 573 no nos llego de la versión 74F...sino 74HC, tendrá algo que ver?:
- The recommended logic family is the Fast TTL 74F-series
- Possible replacements are Advanced Low-Power Schottky 74ALS-series, or CMOS 74ACT-series logic
74LS, 74HCT, 74AHCT series logic might work as well, but have not been tested
Serie 7400
74F – Fast. Fairchild's version of TI's 74AS.
3.4 ns, 6 mW, 4.5–5.5 V. Introduced in 1978.
74HC – High-speed CMOS, similar performance to 74LS, input/output levels not compatible with TTL,
12 ns. 2.0–6.0 V.
Bipolar
74 - Subserie inicial, obsoleta.
74L - Bajo consumo, pero lenta
H - Alta velocidad
S - Schottky, obsoleta
LS - Schottky de bajo consumo
AS - Schottky Avanzada
ALS - Schottky Avanzada de bajo consumo
F - Rápida
CMOS
C - CMOS 4-15V similar a la serie 4000
HC - CMOS alta velocidad, rendimiento similar a LS, 12nS
HCT - Alta velocidad, niveles compatibles con bipolar
AC - CMOS avanzada, rendimiento entre S y F
AHC - CMOS avanzada de alta velocidad, velocidad tres veces superior a HC
ALVC - Bajo voltaje - 1.65 to 3.3V, tpd 2nS
AUC - Bajo voltaje - 0.8 to 2.7V, tpd<1.9nS@1.8V
FC - CMOS rápida, rendimiento similar a F
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"Channel 0 is used by the system to provide a real time clock to interrupt 0. Channel 1 is directly connected to the DMA channel 0 request line and provides timing for the Dynamic RAM refresh. An I/O read from port 0x41 turns refresh on and an I/O write to port 0x43 selecting counter 1 turns refresh off. The channel 2 output is connected to the SPKR signal and provides tone generation."