Va de Retro (Satanás) -- Versión 3.3 SSL

Retroleum escribió:The Upper RAM chips originally used in the Spectrum have a 128-cycle refresh requirement (essentially, a counter from the CPU (its “R” Register) is used to address each row of cells in turn when the CPU is doing other things). This counter is 7-bits wide so counts from 0-127 which is fine for 32Kx1 chips which have 128 rows of 256 cells. However, some 64Kx1 chips require a 256-cycle refresh count (because they have 256 rows of 256 cells) and the Spectrum may not refresh them all correctly** (because the refresh counter only goes from 0-127). Fortunately, many 64Kx1 chips were designed to still need only 128 refresh cycles (they refresh 2 rows per cycle) and such chips will refresh correctly in all Spectrums. It will state in the chip’s datasheet what its refresh requirement is.

** The incompatibility manifests itself when the jumpers are set for OKI chips because of the different way the rows of cells in these chips are addressed. During refresh (and normal access) when the jumpers are set for TI chips, the “AR” pin of each RAM chip receives a fixed high or low (depending on the TI RAM variety jumper setting) so the same half of the 64K chip is refreshed as that being used to store data. However, when the jumpers are set for OKI chips the “AR” pin receives different values: During refresh, the AR pin = CPU register I(6) because the I register is placed on the upper 8 bits of the address bus at this time. The value in I is variable and may or may not match the page of RAM being used for storage. Note: This compatibility issue may not be immediately apparent since a row of bits is also refreshed whenever that row is read by the CPU, but if it has been a while since the previous refresh, the contents will have been lost.

• Retroleum

Lord Raptor escribió: ↑08 Mar 2022, 03:08Pero el refresco de RAM no se hace por medio del registro R del Z80?

4.1) R register and memory refresh

During every first machine cycle (beginning of an instruction or part
of it -- prefixes have their own M1 two), the memory refresh cycle is
issued. The whole of IR is put on the address bus, and the _RFSH is lowered.
It unclear whether the Z80 increases the R register before or after putting
IR on the bus.

The R register is increased at every first machine cycle (M1).

tic escribió: ↑19 Mar 2022, 16:36 No en el +3 lo genera la ula.

tic escribió: ↑30 Mar 2022, 15:25 Al final ha sucedido una especie de milagro raro y por lo visto la ula está bien y el problema era que tenía unas cuantas patas desoldadas al aire.

Lo que tengo roto ahora es la disquetera que tiene el tope de la barra esa del motor roto por lo visto.